Recently, to improve an operating speed of a field effect transistor (FET) or to increase a driving current thereof, various attempts have been made to apply a stress to a channel of the FET. By applying the stress to the channel, the mobility of charges in the channel can be improved, as compared to the case without applying a stress. This technique is disclosed in Japanese Patent Laid-open Application No. 2007-49166 (Patent document 1) or in X. Chen et al., “Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45 nm Technology and Beyond”, 2006 Symposium on VLSI Technology Digest of Technical Papers (Non-patent Document 1).
Further, Patent Document 1 or Non-patent Document 1 discloses a technique referred to as a “Stress Proximity Technique (SPT)” as a way to apply the stress to the channel efficiently. The SPT involves covering top surfaces of source and drain regions and a gate electrode of a FET with a member called a stress liner after removing a pair of sidewall spacers formed on both sides opposite sidewall surfaces of the gate electrode. By removing the sidewall spacers, the stress liner can be positioned more proximal to the channel, whereby a more efficient application of the stress to the channel is enabled.
The sidewall spacers in Patent Document 1 are made of silicon nitride (SiN) or boron silicate glass (BSG) (see paragraph 0017). SiN is removed by using a phosphoric acid based etchant, and BSG is removed by using a fluoric acid based etchant. However, the phosphoric acid based etchant dissolves a silicide layer, and the fluoric acid based etchant dissolves a silicon oxide based film, especially, a device isolation region. The silicide layer is a layer which functions to reduce the resistance of the source and drain regions or the gate electrode. If unevenness in the thickness of the silicide layer is caused as a result of the dissolution of the silicide layer, it would be difficult to obtain a desired transistor characteristic stably and reproducibly even if the transistor works. The device isolation region is a film which separates the source and drain regions of the transistor. If the device isolation region is etched, a circuit failure such as a short between transistors would be caused.
Further, to obtain the desired transistor characteristic stably and reproducibly or to minimize the etching of the device isolation region, the manufacturing process needs to be controlled strictly, and this requirement may be met at the expense of a yield of integrated circuits or a throughput thereof.
Though it is desirable to remove the sidewall spacers selectively against the device isolation region, the gate electrode and the silicide layer, this technique cannot be realized with a conventionally known material. That is, mass production by the SPT under current conditions is still difficult to realize.
Further, Non-patent Document 1 does not disclose anything about the material for the sidewall spacers.